Harnessing Chaos for Computation

John Timmer at Ars Technica explains some fascinating new work on a type of processor that could build on the advantages of FPGAs and provide the speed of more conventional CPUs. Timmer explains the relationship between specialized chips, like DSPs, and traditional CPUs pretty well. In the course of doing so, he notes how a field programmable gate array in many ways represents the best of both, allowing such a chip to dedicate all of its silicon to specialized tasks but able to change the type of task as needed. In reality, FPGAs have limits that make them useful only in certain circumstances, like prototype new chip designs without dedicating fabrication capabilities to building set chips.

The key to this new approach is harness chaos theory.

Those who think of chaos as completely unpredictable are likely to be wondering how unpredictable behavior can be used to perform logic operations. But chaos theory isn’t concerned with unpredictability; instead, it focuses on what are called nonlinear functions, ones where the ultimate output is very sensitive to the initial conditions. When you can control the initial conditions, you can still predict the output.

That ability is at the heart of a chaotic processor. The authors of a recent paper in Chaos describe what they call “chaogates,” which use simple, nonlinear functions to perform logic operations. The basic idea is that, ultimately, you want a logical output, a binary 1 or 0. It’s possible to convert the output of even a complex function into that sort of binary distinction using a strategically placed less than or equal to (<=) operation. If this sort of function is hardwired into the chip, then it’s simply a matter of knowing how to select your inputs so that you get the operation of your choice.

This is very early stage work. While there is a working prototype, it is far from the scale that would make it comparable to existing FPGAs. Timmer notes one aspect of these “chaogates” that already has worked out well, that is they can be re-purposed in about a single clock cycle. If that holds as they are accelerated from the current 30MHz to useful speeds, that would be a considerable advantage.

The biggest barrier is that the existing hardware description languages, used in programming FPGAs, do not apply to these new chips. In addition to proving the theory and building workable prototypes, the researchers have to invent an entirely new, compilable language as well.

Researchers harness chaos theory for new class of CPUs, Ars Technica

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